Faculty

Profile

College / Department

Department of Computer Science and Engineering

Teaching areas

Introduction to Computer Systems. Advanced Embedded Systems Modern Computer Organization Computer Architecture and Organization Embedded Systems VLSI Design Introduction to Information Technology Computer Architecture Microprocessor Interfacing Digital System Design ASIC Design and FPGAs Programming-I

Research areas

Design and Architecture for Racetrack based Hybrid Memory Systems System simulator for heterogeneous processing and memory components Spin Orbit Torque memory for cache & multicore processor applications Multi-core simulation Framework for caches and main memory

Education

PhD, Computer Science, Karlsruhe Institute of Technology, Germany, 2015

MS, Electronic Engineering, Ghulam Ishaq Khan Institute, Pakistan, 2006

Bachelor, Computer Systems, NED University, Pakistan, 2003

Professional experience

Assistant Professor, Institute of Space Technology, 2017 - 2024

Post-doctoral Researcher, Technical University Dresden, Germany, 2016 - 2017

Post-doctoral Researcher, Karlsruhe Institute of Technology, Germany, 2015 - 2016

Researcher, Karlsruhe Institute of Technology, Germany, 2008 - 2015

Lecture, Mohammad Ali Jinnah University, Pakistan, 2006 - 2008

Contact

[email protected]

+971 6 515 4818

Fazal Hameed

Visiting Assistant Professor

PhD, Karlsruhe Institute of Technology, Germany

Fazal Hameed received his Ph.D.(Dr.-Ing.) degree in computer science from the Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany, in 2015. He joined the chair for Compiler Construction at the TU Dresden (Dresden, Germany) as Post-doctoral researcher in March 2016. Before, he worked on a similar position at the Chair of Dependable and Nano Computing (CDNC) Karlsruhe Institute of Technology (KIT), Germany. He is currently affiliated with American University of Sharjah, UAE. He mainly works in the computer architecture area with a primary focus on memories. Mr. Hameed was a recipient of the CODES+ISSS 2013 Best Paper Nomination for his work on DRAM cache management in multicore systems. He has served as an External Reviewer for maj...

Publications

Asif Ali Khan, Fazal Hameed, Taha Shahroodi, Alex K. Jones And Jeronimo Castrillon . Efficient Memory Layout for Pre-Alignment Filtering of Long DNA Reads Using Racetrack Memory, Ieee Computer Architecture Letters, 19 January (1st Quarter/Winter) 2024

Asif Khan, Sebastien Ollivier, Fazal Hameed, Jeronimo Castrillon And Alex Jones. DownShift: Tuning Shift Reduction with Reliability for Racetrack Memories, Ieee Transactions On Computers, 1 September 2023

Christian Hakert, Asif Khan, Kuan Chen, Fazal Hameed, Jeronimo Castrillon And Jian Chen. ROLLED: Racetrack Memory Optimized Linear Layout and Efficient Decomposition of Decision Trees, Ieee Transactions On Computers, 1 May 2023

Fazal Hameed, Moazam Maqsood And Syed Irtaza. An energy-efficient cache replacement policy for ultra-dense racetrack memory, Journal Of Systems Architecture, 1 April (2nd Quarter/Spring) 2023

Fazal Hameed And Jeronimo Castrillon. BlendCache: An Energy and Area Efficient Racetrack Last-Level-Cache Architecture, Ieee Transactions On Computer-aided Design Of Integrated Circuits And Systems, 1 December 2022

Fazal Hameed, Asif Khan And Jeronimo Castrillon. ALPHA: A Novel Algorithm-Hardware Co-Design for Accelerating DNA Seed Location Filtering, Ieee Transactions On Emerging Topics In Computing, 1 January (1st Quarter/Winter) 2022

Fazal Hameed, Asif Khan, Sebastien Ollivier, Alex Jones And Jeronimo Castrillon. DNA Pre-Alignment Filter Using Processing Near Racetrack Memory, Ieee Computer Architecture Letters, 1 January (1st Quarter/Winter) 2022

Christian Hakert, Asif Khan, Kuan Chen, Fazal Hameed, Jeronimo Castrillon And Jian Chen. BLOwing Trees to the Ground: Layout Optimization of Decision Trees on Racetrack Memory, 5 December 2021

Fazal Hameed, Asif Khan And Jeronimo Castrillon. Improving the Performance of Block-based DRAM Caches Via Tag-Data Decoupling, Ieee Transactions On Computers, 1 November 2021

Asif Khan, Norman Rink, Fazal Hameed And Jeronimo Castrillon. Optimizing Tensor Contractions for Embedded Devices with Racetrack and DRAM Memories, Acm Transactions On Embedded Computing Systems, 1 November 2020

Robin Blasing, Asif Khan, Panagiotis Filippou, Chirag Garg, Fazal Hameed, Jeronimo Castrillon And Stuart Parkin. Magnetic Racetrack Memory: From Physics to the Cusp of Applications within a Decade, Proceedings Of The Ieee, 1 August 2020

Asif Khan, Andres Goens, Fazal Hameed And Jeronimo Castrillon. Generalized Data Placement Strategies for Racetrack Memories, 1 March 2020

Asif Khan, Fazal Hameed, Robin Bläsing, Stuart Parkin And Jeronimo Castrillon. Shiftsreduce: Minimizing shifts in racetrack memory 4.0, Acm Transactions On Architecture And Code Optimization, 1 December 2019

Fazal Hameed And Jeronimo Castrillon. A novel hybrid DRAM/STT-RAM last-level-cache architecture for performance, energy, and endurance enhancement, Ieee Transactions On Very Large Scale Integration (vlsi) Systems, 1 October (4th Quarter/Autumn) 2019

Joonas Multanen, Pekka Jaaskelainen, Asif Khan, Fazal Hameed And Jeronimo Castrillon. SHRIMP: Efficient Instruction Delivery with Domain Wall Memory, 1 July (3rd Quarter/Summer) 2019

Asif Khan, Fazal Hameed, Norman Rink And Jeronimo Castrillon. Optimizing tensor contractions for embedded devices with racetrack memory scratch-pads, 23 June 2019

Asif Khan, Fazal Hameed, Robin Blasing, Stuart Parkin And Jeronimo Castrillon. RTSim: A Cycle-Accurate Simulator for Racetrack Memories, Ieee Computer Architecture Letters, 1 June 2019

Sarath Nai, Rajendra Bishnoi, Mohammad Golanbari, Fabian Oboril, Fazal Hameed And Mehdi Tahoori. VAET-STT: Variation Aware STT-MRAM Analysis and Design Space Exploration Tool, Ieee Transactions On Computer-aided Design Of Integrated Circuits And Systems, 1 July (3rd Quarter/Summer) 2018

Fazal Hameed, Asif Khan And Jeronimo Castrillon. Performance and energy-efficient design of STT-RAM last-level cache, Ieee Transactions On Very Large Scale Integration (vlsi) Systems, 1 June 2018

Asif Khan, Fazal Hameed And Jeronimo Castrillon. NVMain extension for multi-level cache systems, 22 January (1st Quarter/Winter) 2018

Fazal Hameed, Christian Menard And Jeronimo Castrillon. Efficient STT-RAM last-level-cache architecture to replace DRAM cache, 2 October (4th Quarter/Autumn) 2017

Fazal Hameed And Jeronimo Castrillon. Rethinking on-chip DRAM cache for simultaneous performance and energy optimization, 11 May 2017

Fabian Oboril, Fazal Hameed, Rajendra Bishnoi, Ali Ahari, Helia Naeimi And Mehdi Tahoori. Normally-OFF STT-MRAM Cache with Zero-Byte Compression for Energy Efficient Last-Level Caches, 8 August 2016

Fazal Hameed And Mehdi Tahoori. Architecting STT Last-Level-Cache for performance and energy improvement, 25 May 2016

Fazal Hameed, Lars Bauer And Jorg Henkel. Architecting On-Chip DRAM Cache for Simultaneous Miss Rate and Latency Reduction, Ieee Transactions On Computer-aided Design Of Integrated Circuits And Systems, 1 April (2nd Quarter/Spring) 2016

Fazal Hameed, Lars Bauer And Jörg Henkel. Reducing latency in an SRAM/DRAM cache hierarchy via a novel tag-cache architecture, 1 January (1st Quarter/Winter) 2014

Fazal Hameed, Lars Bauer And Jörg Henkel. Adaptive cache management for a combined SRAM and DRAM cache hierarchy for multi-cores, 1 January (1st Quarter/Winter) 2013

Fazal Hameed, Lars Bauer And Jörg Henkel. Reducing inter-core cache contention with an adaptive bank mapping policy in DRAM cache, 1 January (1st Quarter/Winter) 2013

Fazal Hameed, Lars Bauer And Jörg Henkel. Simultaneously optimizing DRAM cache hit latency and miss rate via novel set mapping policies, 1 January (1st Quarter/Winter) 2013

Fazal Hameed, Lars Bauer And Jörg Henkel. Dynamic cache management in multi-core architectures through run-time adaptation, 1 January (1st Quarter/Winter) 2012

Fazal Hameed, Mohammad Al Faruque And Jörg Henkel. Dynamic thermal management in 3D multi-core architecture through run-time adaptation, 31 May 2011

Grants and sponsorships

Grant, Design and Architecture for Racetrack based Hybrid Memory Systems proposal, German Research Foundation, September 2020 - August 2022

Grant, Inspire Grant, Technical University Dresden, - December 2017

Awards and Honors

Best paper nomination, CODES+ISSS’13 conference, CODES+ISSS’13 best paper nomination for the paper Reducing Inter-Core Cache Contention with an Adaptive Bank Mapping Policy in DRAM Caches, 2013

Research Student Award, Karlsruhe Institute of Technology, Research Student Awards (RSA) from KIT, Summer 2012., 2012

Second Position in Master, GIK Institute, 2nd position in Master of Science (M.S.) in 2006 (GIK Institute, Topi Pakistan), 2006